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What’s New in Xilinx ISE Design Suite 13.1
Please see the PlanAhead section in Chapter 2, “Important ISE Design Suite 13 Release
Information,” for details of what’s new in the following areas:
FPGA Editor
?
New Lock Layers toolbar button, which locks the current layer visibility settings for
all zoom levels.
iMPACT
?
New SPI/BPI programming support:
?
?
?
Numonyx P30 bottom boot is supported, in addition to top boot.
Winbond W25Q is supported up to 128Mb.
Winbond W25Q support for the CV revision has been added.
ChipScope Pro
?
ChipScope Pro HDL (VHDL and Verilog) Debug probe using PlanAhead and XST
Synthesis flow
?
?
Enable users to mark debug nets on HDL or XCF constraint file
When MARK_DEBUG attribute is used:
-
-
Nets are preserved (not optimized away)
Nets appear in the ChipScope view in the PlanAhead view so users can
assign to debug cores
?
ChipScope Pro HDL Debug probe using PlanAhead and Synplify Synthesis flow
?
?
Enable users to mark debug nets on HDL (VHDL and Verilog) or SDC
When MARK_DEBUG attribute is used:
-
-
Nets are preserved (not optimized away)
Nets appear in the ChipScope view in the PlanAhead view so users can
assign to debug cores
?
BERT for Virtex?-6 GTX and GTH available in PlanAhead and ChipScope Flow
?
Also added low- and mid-range line rate support for IBERT V6 GTH
?
Startup Trigger Mode
?
?
Using Project Navigator, Core Inserter, and Analyzer Tools
Using PlanAhead and Analyzer Tools
?
BERT sweep test plot GUI
?
?
Built-in graphical viewer of IBERT sweep test results for Virtex?-6 GTX/GTH
FPGA transceivers
Standalone graphical viewer for offline analysis of IBERT sweep test results for
Virtex?-6 FPGA GTX/GTH, Spartan?-6 FPGA GTP, and Virtex?-5 FPGA GTX
transceivers
?
Tutorials:
?
?
PlanAhead Tutorial: Debugging with ChipScope Analysis
ChipScope IBERT: Basic IBERT design flow
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
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